ABR Patent US12688397: The AI Chip That Runs a Voice Assistant on 35mW
💡 Applied Brain Research's US patent 12688397, granted 21 July 2026, protects a partitionable chip architecture for state-space neural networks that runs full-vocabulary speech recognition at under 35mW - up to 100 times more power-efficient than competing approaches. The commercial product, the TSP1 (Time-Series Processor 1), is the world's first single chip capable of full-vocabulary voice AI without cloud connectivity. The patent signals that brain-inspired computing has crossed from research curiosity to commercial hardware reality.
What US12688397 Actually Claims
On 21 July 2026, the United States Patent and Trademark Office granted patent US12688397 to Applied Brain Research Inc. (ABR), a Canadian edge AI company founded by computational neuroscientist Christopher Eliasmith and his colleagues at the University of Waterloo. The three inventors - Gurshaant Singh Malik, Aaron Russell Voelker, and Eliasmith - describe a "partitionable digital hardware system for implementing recurrent neural networks."
In plain terms, the patent covers a chip fabric that can be divided into independent processing tiles, each capable of running its own recurrent neural network workload simultaneously. When you need speech recognition, certain tiles handle audio; when you need gesture classification at the same moment, other tiles handle that - all on a single die drawing under 35 milliwatts total. This differs fundamentally from how a GPU processes neural networks: instead of batching everything through a shared pool of compute units, ABR's architecture routes data through a network of stateful tiles that evolve over time, matching the temporal dynamics of real-world signals. The table below gives the key facts at a glance - the kind of cross-jurisdiction fact sheet that makes patent translation essential.
| Field | Detail |
|---|---|
| Patent number | US 12,688,397 |
| Title | Partitionable digital hardware system for implementing recurrent neural networks |
| Assignee | Applied Brain Research Inc. (Waterloo, Ontario, Canada) |
| Inventors | Gurshaant Singh Malik; Aaron Russell Voelker; Christopher David Eliasmith |
| Grant date | 21 July 2026 |
| Jurisdiction | United States (USPTO) |
| Technology category | Neuromorphic computing / edge AI hardware |
| Commercial product | TSP1 (Time-Series Processor 1) - dev kits available 2026 |
Why AI Got Stuck in the Cloud in the First Place
Every time you speak to a smart device and watch it pause before responding, you are watching the memory wall at work. Modern AI voice assistants run transformer-based models, which require every input token to attend to every other token in the sequence. That attention mechanism scales with the square of the sequence length - an O(n²) memory demand that a battery-powered chip simply cannot sustain at any useful vocabulary size. The result is that virtually all voice AI ships the hard work to the cloud, adding 100-500ms of latency, raising privacy risks, and requiring continuous connectivity.
For hearing aids, AR glasses, or industrial sensors, this is a fundamental dealbreaker. A hearing aid must process speech in under 10 milliseconds to avoid audible delay - it cannot wait for a round trip to a data centre. The entire on-device AI future has been blocked by the transformer's memory appetite. That is not an engineering limitation but a mathematical one, which means the fix has to be mathematical too. And that brings us to the Legendre Memory Unit.
The Legendre Memory Unit: the Mathematics Behind the Patent
The Legendre Memory Unit (LMU) is ABR's foundational invention, developed by Aaron Voelker and Chris Eliasmith at Waterloo and published at NeurIPS 2019. Instead of storing past context as raw activations (as attention does), the LMU compresses the entire history of a signal into a small, fixed-size set of Legendre polynomial coefficients. The Legendre polynomials are a family of mathematical functions that tile across time with zero overlap, so a fixed vector of perhaps 100 numbers can encode an entire conversation history regardless of how long the conversation runs. Memory complexity drops from O(n²) to O(1) per timestep - constant, independent of sequence length.
The LMU belongs to the broader family of state-space models (SSMs), which drew enormous research attention after the Mamba architecture showed in 2023 that SSMs could match transformer benchmarks at a fraction of the compute. ABR's patent translates this mathematical insight into silicon: the partitionable tile architecture is specifically designed to implement the LMU's recurrence update in hardware, running multiple SSM workloads on the same die without shared-state conflicts. The patent covers both the partitioning logic and the data path optimised for SSM weights and state updates - a direct line from mathematical research to protected IP. But what exactly does "partitionable" mean in hardware terms?
Partitionable: the Key Claim in US12688397
The word "partitionable" in the patent title is not incidental - it is the core innovation. Most neural network chips, from Google's TPU to BrainChip's Akida, are designed to run one workload at a time across the entire die. ABR's architecture allows the chip to be logically subdivided at runtime, assigning different tile groups to different neural network tasks simultaneously. Two direct consequences follow.
First, it enables real-time multi-task inference on a single milliwatt-range chip: voice recognition and acoustic event detection can run in parallel without time-multiplexing, cutting latency. Second, it enables modular deployment: device makers can allocate a different number of tiles per task depending on model complexity, rather than needing separate silicon for each application. For a startup penetrating the fragmented wearable, medical, and automotive sensor markets, this flexibility is as commercially important as raw efficiency. The patent locks in this partitioning approach as ABR's core IP moat. The next question is: where does this sit in the broader innovation map?
Where This Patent Sits in the Wider Innovation System
US12688397 lands at the intersection of three concurrent waves. The first is the edge AI push: as cloud AI costs rise and privacy regulations tighten in healthcare and finance, companies from Apple to Qualcomm are racing to move inference onto device. The second is the SSM revolution: state-space architectures have become a credible alternative to transformers for sequential tasks, with the hardware advantage of constant memory footprint. The third is neuromorphic IP acceleration: neuromorphic computing chip patents surged 401% in 2025 alone (Patsnap, data 2025), as every major chip company begins filing brain-inspired hardware claims.
ABR is not alone in the neuromorphic space. Intel's Loihi 2 platform, deployed at Sandia National Laboratories as "Hala Point" with 1.15 billion simulated neurons, uses spiking neural networks (SNNs). BrainChip's Akida is already in commercial edge devices, also SNN-based. What distinguishes ABR is the SSM approach: the TSP1 implements smooth recurrent updates using the LMU, which aligns better with standard trained neural network models, simplifying the model-to-chip deployment pipeline compared to SNN conversion. The partitioning patent protects this pipeline as proprietary IP - and the people behind it deserve a closer look.
Who Built This - and Who It Now Threatens
Applied Brain Research was founded in Waterloo, Ontario, as a spinout from Christopher Eliasmith's Computational Neuroscience Research Group. Eliasmith's team built "Spaun" in 2012 - then the world's most complex functional brain model - and developed the Semantic Pointer Architecture underlying the LMU. Kevin Conley, ABR's CEO, frames the commercial challenge directly: voice is becoming the default interface for the next wave of edge devices, but cloud-dependent voice AI delivers a poor experience for always-connected, latency-sensitive applications. The seed round closed oversubscribed in January 2026, led by Two Small Fish Ventures with Eva Lau joining the board. TSP1 developer kits are now commercially available.
The patent places real pressure on several incumbents. Qualcomm and ARM, who supply the AI accelerators in virtually every smartphone, face an architectural challenge: if SSM chips handle always-on voice and sensor fusion at 35mW on standalone silicon, the need for always-on NPUs baked into application processors weakens. Cloud AI providers - Amazon, Google, Microsoft - lose inference revenue if voice queries never leave the device. And traditional hearing aid makers, whose premium products run at 1-2mW but cannot execute modern AI, face disruption if ABR's power envelope continues to shrink toward theirs. The 401% jump in neuromorphic patents in 2025 is the clearest sign that incumbents have noticed.
So What Does It Mean for Us?
US12688397 is a quiet patent: no explosion, no record transistor count, no dramatic superintelligence claim. What it represents instead is a milestone in the commercialisation of brain-inspired computing: the point where a mathematically rigorous alternative to the transformer made it not only onto silicon, but onto silicon that ships in developer kits in 2026, backed by oversubscribed funding, with a clear product roadmap toward hearing aids, AR glasses, industrial sensors, and automotive voice interfaces. The neuromorphic chip market is projected to grow from $510M in 2026 to $4.08B by 2031 at 51.57% CAGR (MarketsandMarkets, data 2026), and ABR's patent is a key piece of the IP foundation for that growth.
For the translation and IP localization industry, US12688397 is a useful illustration of why frontier hardware patents are so demanding to render across languages. The claims invoke Legendre polynomial mathematics, recurrent state dynamics, partitionable compute fabrics, and edge inference pipelines simultaneously. A translator who does not understand what a stateful tile is, or why "partitionable" is the key word, cannot faithfully render the scope of the claim - and a claim rendered unfaithfully is an unenforceable claim. As ABR seeks international protection, the precision of each technical translation will directly determine the breadth of the IP moat in each jurisdiction.
FAQ
What is a state-space model, and how does it differ from a transformer?
Transformers use an attention mechanism that compares every part of an input sequence with every other part, making memory grow with the square of the sequence length. State-space models like the LMU compress the entire history into a small fixed-size vector updated at each timestep, keeping memory constant regardless of sequence length. This makes SSMs far better suited to low-power edge chips where memory bandwidth is limited.
What does "partitionable" mean in this patent?
"Partitionable" means the chip's compute fabric can be logically divided into independent groups of tiles, each running a different neural network task simultaneously. One partition handles voice recognition while another handles gesture detection - all on a single die. Most competing chips run one workload across the entire hardware at a time, forcing either resource waste or time-multiplexing with added latency.
What is the TSP1 chip, and what applications does it target?
TSP1 (Time-Series Processor 1) is ABR's first commercial chip, implementing the patented partitionable SSM architecture. It runs full-vocabulary automatic speech recognition at under 35mW - 10-100 times more efficient than alternatives - without cloud connectivity. Developer kits became available in early 2026. Target applications include hearing aids, AR glasses, wearables, robotics, medical devices, and automotive voice interfaces where latency and power matter most.
How does ABR compare to Intel Loihi or BrainChip Akida?
All three are neuromorphic chips targeting low-power AI, but they use different architectures. Intel Loihi 2 and BrainChip Akida use spiking neural networks (SNNs) that process only when a signal changes. ABR's TSP1 implements state-space models using smooth recurrent updates, which are more directly compatible with standard trained models, making deployment simpler. ABR's patent covers the partitionable SSM hardware fabric - a distinct and protected approach.
Why does patent translation matter for a chip patent like US12688397?
This patent blends Legendre polynomial mathematics, hardware architecture terms (partitionable tile fabric), and legal claim language simultaneously. Precise patent translation and technical translation are essential for international filing and enforcement. A mistranslation of a key claim term can narrow the legal scope of protection in that jurisdiction, making the patent easier for competitors to design around.
Sources
Open Neuromorphic: TSP1 Time-Series Processor - Applied Brain Research (2026) | Newswire: ABR Closes Seed Funding Round, January 2026 | EE Times: ABR Demos First Silicon for State-Space Models (2025) | MarketsandMarkets: Neuromorphic Chip Market Report (data 2026) | Patsnap: Neuromorphic Computing Chip Patents Surge 401% in 2025
About the Author
Dao Huy (Lucas) is a professional translator with over seven years of experience specializing in technical, patent, and IP translation between English, Chinese, French, and Vietnamese. He works extensively with semiconductor, AI hardware, and engineering documentation, where precise terminology determines whether a patent claim is enforceable or escapable.
If your organization needs patent translation, IP translation, or technical document localization into Vietnamese - including chip architecture filings, AI hardware specifications, and software localization - reach out for a quote at daohuy.com.
Written by Dao Huy (Lucas), Vietnamese translator & localization specialist (EN · ZH · FR → Vietnamese). See translation services →