AMD Patent US12688138: The Active Bridge Chiplet Powering the AI Chip Wars

💡 Advanced Micro Devices (AMD) just had US patent US12688138 granted by the USPTO on July 21, 2026, covering an "Active Bridge Chiplet with Integrated Cache" - a silicon die that simultaneously connects multiple GPU compute chiplets and hosts a unified last-level cache, making the entire multi-die system appear as one device to software. This patent underpins the IO-die design inside AMD's Instinct MI300X, which packs 256 MB of shared last-level cache and claims 10-60% performance advantages over NVIDIA's H100 on large language model workloads. The chiplet architecture revolution is being locked down in IP, one patent at a time.

2025$54.5B

2026$66.6B

2034$350.8B

Field	Detail
Patent number	US12688138
Title	Active Bridge Chiplet with Integrated Cache
Assignee	Advanced Micro Devices, Inc. (AMD)
Inventors	Skyler J. Saleh; Ruijin Wu (San Diego, CA)
Priority filing	September 27, 2019 (parent application US16/585,452)
Grant date	July 21, 2026
Jurisdiction	USPTO (United States)
CPC classification	G06F 13/4027 (Bus Bridges)
Core claim	Active bridge die connecting compute chiplets while hosting a shared, coherent last-level cache accessible by all connected chiplets
Commercial implementation	AMD Instinct MI300X: 4 IO bridge dies + 8 compute XCDs, 256 MB Infinity Cache shared LLC

What AMD's Patent US12688138 Actually Claims

The patent describes a chiplet architecture where a dedicated active bridge die performs two jobs simultaneously. First, it serves as a high-bandwidth crossbar switch connecting multiple compute chiplets - the small silicon tiles that handle actual GPU computation. Second, and more importantly, it hosts a unified last-level cache (LLC) that is accessible to every connected compute chiplet through the bridge, as if the entire multi-die system were a single device. From a software developer's perspective, the multi-die GPU presents one flat address space: no tile-mapping, no per-die cache management.

Inventors Skyler J. Saleh and Ruijin Wu filed the original concept at the USPTO on September 27, 2019, when AMD was still a distant challenger to NVIDIA's GPU dominance. The idea published as application US20210097013A1 in April 2021 and received an initial grant in November 2022 (US11507527B2). The continuation patent US12688138, covering expanded or refined claim scope, received its grant stamp on July 21, 2026 - almost exactly as the MI300 series that implements this design reaches its second generation. The CPC classification G06F 13/4027 captures the essence: this is an active, cache-carrying silicon bridge, not a passive interposer.

A patent covering "a bridge with a cache" sounds like a narrow engineering detail. The problem it solves, however, is why chiplets struggled to replace monolithic GPU dies for most of the past decade.

The Chiplet Fragmentation Problem: Why Cache Coherence Is Hard Across Dies

When you slice a GPU into multiple chiplets, you immediately break the shared memory model that application software relies on. Each compute die wants fast, private local cache access. But if die A caches a memory address and die B reads the same address independently, you get a stale-read coherence failure. Solving that problem in software requires programmers to track which physical die owns which memory slice - an enormous burden for workloads that stream data dynamically across compute units, exactly as neural-network training does.

The conventional answer was a passive silicon interposer: a substrate connecting dies with no logic of its own. Passive interposers cannot manage cache coherence; they are wires, not controllers. AMD's patented solution is to put the cache management logic inside the bridge die itself. The active bridge contains the crossbar switch for die-to-die traffic AND the LLC controller, so every compute chiplet reads from and writes to a single logical cache, with coherence maintained inside the bridge hardware. No software changes required.

Solving coherence in silicon requires a bridge die that knows the cache - and that bridge die needs an entire advanced-packaging supply chain to exist at the bandwidth required.

What This Patent Depends On: The Advanced-Packaging Supply Chain

An active bridge chiplet cannot run on a conventional PCB. It requires 2.5D or 3D packaging - placing multiple dies in intimate proximity with micro-bump or through-silicon-via (TSV) interconnects - to deliver the internal bandwidth that makes the shared cache non-limiting. In AMD's MI300X implementation, TSMC's CoWoS (Chip-on-Wafer-on-Substrate) process places 8 compute XCDs and 4 IO bridge dies in a single package. Each IO bridge die connects to two stacks of HBM3 memory at 665 GB/s per stack, and the 4 IO dies together offer 5.3 TB/s of aggregate HBM bandwidth with 128 memory channels total.

The IO dies themselves are fabricated at 6 nm (TSMC), while the compute XCDs use 5 nm. The Infinity Cache inside the IO dies delivers 17 TB/s of peak internal bandwidth at 2.1 GHz - roughly three times the HBM bandwidth, so the cache acts as a genuine high-speed buffer between compute and memory. Without TSMC's CoWoS packaging capability and leading-edge process access, this patent's concept would remain theoretical.

Once advanced packaging solves the physical problem, the active bridge design unlocks a class of AI compute performance that was previously impossible from a single package.

What It Unlocks: Coherent AI Compute in the Multi-Die Era

The MI300X built around this active bridge architecture holds 192 GB of HBM3e memory - more than twice what NVIDIA's H100 can access - backed by the 256 MB Infinity Cache in the four IO bridge dies. That cache is enormous by GPU standards: NVIDIA's H100 has 50 MB of shared L2 cache on a monolithic die. AMD's active bridge gives the MI300X five times more last-level cache, distributed across four bridge dies but unified logically by the patented coherence mechanism.

The practical result: large language models with tens of billions of parameters can fit entirely in on-package memory and cache, eliminating the latency of constant round-trips to external DRAM. AMD's own benchmarking claims 10-60% performance advantages over the H100 across LLM and inference workloads (Hot Hardware, 2023/2026). The MI300A variant, combining 3 CPU chiplets, 6 GPU chiplets, and the same 4 IO bridge dies, goes further: AMD claims a 4x performance advantage over H100 in OpenFOAM HPC benchmarks.

The capabilities are AMD's achievement, but who the patent ultimately threatens is the company that bet against chiplet GPUs for years.

Who Built It: AMD's Chiplet-First Decade

AMD adopted chiplets for CPUs in 2017 with the "Zen" Ryzen architecture, separating the performance-critical compute complex die (CCD) from a shared I/O die - a move that let AMD fabricate the hot compute cores on an advanced node while keeping I/O on a cheaper, mature process. That decision rescued AMD from the edge of insolvency and turned EPYC into a leading server CPU by 2022.

The active bridge chiplet patent takes the chiplet philosophy from CPUs - where data consistency across dies is a solved problem in existing multi-core software - to GPUs, where the shared cache problem is harder and the performance stakes higher. The 2019 filing reflects AMD's decision to bet that chiplet GPUs would eventually match or exceed monolithic GPUs: a bet the MI300 series validated when it launched in late 2023. AMD now holds a growing chiplet IP portfolio, with US12688138 adding to the defensive moat around its MI-series architecture just as rivals scramble to close the gap.

The value of that moat depends entirely on how competitors respond - whether they build their own bridge chiplets or choose a different architectural path.

Who It Threatens: NVIDIA's Monolithic Die Approach

NVIDIA's H100 and H200 are large monolithic GPU dies: all compute and all cache on one chip. This made sense when Moore's Law delivered a performance generation every two years - just shrink the die. But leading-edge wafer yields on 4-5 nm dies above a certain size fall sharply, making the economics of 80-billion-transistor monolithic dies increasingly difficult. NVIDIA's response in the Blackwell architecture (GB100) is to use NVLink die-to-die bonding - a different bridge approach that does not replicate AMD's active bridge LLC architecture.

Intel's Ponte Vecchio GPU took an extreme chiplet approach with 47 tiles, but suffered from yields and was eventually discontinued. AMD's active bridge with a central unified cache is architecturally simpler and better suited to the coherence problem. The July 2026 grant narrows the design space further: any rival building an active bridge-plus-cache chiplet GPU must now either design around AMD's patent or negotiate a cross-license. That is not a fatal constraint, but it is a real IP cost in an industry that spends billions per year on foundry access and packaging tooling.

Beyond today's GPU wars, the deeper implication is what this architecture enables as chiplets migrate from data-center accelerators to automotive SoCs, edge devices, and the next generation of consumer GPUs.

The Bigger Picture: Chiplets as the New Moore's Law - and Why Patent Translation Follows

The chiplet paradigm is becoming the default architecture for any high-performance chip that cannot be fabricated cost-effectively on a single leading-edge die. The global chiplet market was valued at USD 54.49 billion in 2025 and is projected to reach USD 350.79 billion by 2034 at a CAGR of 23.1% (Fortune Business Insights, 2025). Every major AI accelerator, every high-end server CPU, and a growing number of automotive compute SoCs are moving in this direction.

As the chiplet ecosystem expands globally, the IP landscape hardens. AMD's US12688138 was granted by the USPTO - but AMD's chips are manufactured in Taiwan (TSMC), sold in South Korea, Japan, China, and Europe, and compete against companies headquartered in each of those markets. To enforce this patent globally, AMD needs equivalent filings translated and prosecuted in each relevant jurisdiction. A patent translation error in a cache-coherence claim - mistranslating the scope of "shared last-level cache accessible by all compute chiplets" in Japanese or Chinese - can render the patent unenforceable against the most important competitors. Precise technical patent translation is not optional for a company whose product revenue depends on this IP.

From one transistor-level design idea filed in California in 2019, we arrive here: a July 2026 grant that defines the legal landscape for multi-die GPU architectures in the coming decade.

So What Does It Mean for Us?

AMD's US12688138 matters as more than a single semiconductor patent. It is a marker: the industry has permanently shifted to multi-die, chiplet-based architectures, and the IP covering those architectures is being locked down in real time. The active bridge chiplet with integrated cache is now one of AMD's cleaner, more fundamental pieces of semiconductor IP - a concept that competitors must respect in design, and that AMD can license or assert globally.

For engineers and product planners building AI accelerators, edge compute silicon, or next-generation automotive processors, this patent defines a design boundary. For translation professionals and IP teams, it is a reminder that semiconductor innovation begins in patent filings - and that cross-market enforcement of those filings requires flawless technical translation to hold up before a patent examiner in Tokyo, Seoul, Munich, or Beijing. The chiplet revolution is the post-Moore's-Law answer to building faster computers, and AMD's patent is one brick in the IP fortress rising around it.

FAQ

Sources
USPTO Official Gazette Week 29 - Patents issued July 21, 2026
Google Patents - US20210097013A1 parent application (2021)
HotHardware - AMD Instinct MI300 Architecture Deep Dive (2023)
Chips and Cheese - AMD CDNA 3 Compute Architecture (2023)
Fortune Business Insights - Chiplets Market Size Report (2025)

About the author

Dao Huy (Lucas) is a professional translator with over 7 years of experience in technical, patent, and IP translation from English, Chinese, and French into Vietnamese. His work covers semiconductor IP filings, engineering documentation, and technology product localization - fields where precision in rendering claims about cache architectures and interconnect protocols matters as much as language fluency. The chiplet IP wave is creating a global surge in semiconductor patent filings, every one of which needs faithful translation to enforce across markets.

Need patent translation for a semiconductor, AI, or advanced-packaging filing? Looking for accurate English to Vietnamese technical translation or technology localization for your documentation? Contact Lucas at daohuy.com for a free quote.